JaguarRoute

  Benchmarks

XPlace and XRoute are the placer and router of X company, one of the top 3 EDA compaines, and wire count(wc) , wire length(wl), and via count(vc) are the three major numbers demonstrated in the following.

Case 0: xyz_0s: from XPlace/XRoute the fully routed design from XPlace/XRoute from X company

Case 1: xyz_1s: from XPlace/JRoute we rip up all signal wires and reroute them with JRoute

Case 2: xyz_2s: from JPlace/JRoute we run JPlace to re-place the cells with no clock pins before running JRoute

design d65 [65nm, 600+k nets]

wc0 =12301281
len0 =56105480 (um)
via0 =9940780
len0+via0 =66046260

wc1 =7700985 [-37.4%]
len1 =54974032 [-2.0%]
via1 =7666704 [-22.9%]
len1+via1 =62640736 [-5.2%]

wc2 =7419845 [-39.7%]
len2 =52347212 [-6.7%]
via2 =7547916 [-24.1%]
len2+via2 =59895128 [-9.3%]

wc0 =1369079
len0 =2052499
via0 =1141567
len0+via0 =3194066

wc1 =1065274 [-22.2%]
len1 =2042352 [-0.5%]
via1 =969186 [-15.1%]
len1+via1 =3011538 [-5.7%]

wc2 =1092201 [-20.2%]
len2 =2012127 [-2.0%]
via2 =964779 [-15.5%]
len2+via2 =2976906 [-6.8%]

From above data, it is clear that in shortening the wire length, the placer plays an important role in above two designs.

note : Please keep in mind that all P&R compliances with high-end technology node, like 2nm or 3nm, in case 0 may be broken in our P&R in generaing case 1 and case 2, which mainly focuses on shortening the wires and the rules which have been implemented, up to 45nm. It will be up to the user to decide the quality of P&R in case 0, which will be used to creating case 1 and case 2.

figure 1: comparison of case0, case1, and case2, from left to right, for the best net in design d28

Note: This is a 3-pin net. Apparenly, case 1 is better than case 0. After re-placement in case 2, three pins are placed much close to each other and it further cuts the wire length dramatically.

Figure 2: comparison of case 0, case 1, and case 2, from left to right, for the worst net in design d28

Note: apparently, case 1 loses to case 0. After re-placement in case 2, the result has improved a lot.

figure 3: comparison of case0, case1, and case2, from left to right, for the best net in design d65

Figure 4: comparison of case 0, case 1, and case 2(longer, zoom out more), from left to right, for the worst net in design d65

Note: in figure 4, apparently, both case 1 and case 2 lose to case 0.

Figure 5: the comparison of case 0 and case 1 for the best net in design d65

Figure 6: the comparison of case 1 and case 2 for the best net in design d65

note : chart_per[x] = y
--top portion: the latter is longer, x percent of the former.
--bottom portion: the former is longer, x percent of the latter.
i.e. the more nets at the bottom, the better the latter case.

Note 1: compare_01 represents the outperformance of JRoute over XRoute
compare_12 represents the outperformance of JPlace over XPlace
compare_02 represents the outperformance of JP&R over XP&R

Note 2: for the convenience of viewing and comparison purpose in GUI, temporarily, via count is ignored in length calculation. Because JRoute uses much less number of vias, if they are included, the above numbers will be much better for JP&R.

Q: your comparison data is biased and not comparing apple to apple, because case 0 is tape-out ready design, free of ALL violations, and case 1 & 2 may have lots of violations in high-end nano-meter(nm) rule checker for tape-out even though your wire length and via count is better.

A: Yes, it is true. According to above data in two designs, we believe our P&R engine performs much better than the ones on the market. So we encourage the user to use their creativity to combine the use of our P&R booster and their exsiting tool to create better results. One example is to use JPlace to re-place the placement from XPlace and do the remaining jobs in the existing tool flow. Another example is to use our P&R booster to create the best framework of P&R, then use their existing tool to fix all high-end nm special rule violations for their tape-out purpose. We believe the above way may achieve better results. Logically, it makes sense and is possible, if most of the violations are local and need minor rip-up and re-route.

Q: We are in high-end nm technology node now, like 2 or 3 nm, and your tool is far behind (between 45nm and 65nm), how can you help us?

A: Same as before, we simply parse all special rules, intentially ignoring some of them, and generate the best framework of P or P&R for you to feed into your flow and HOPE your tape-out journey will be easier and the result will be better.

1. In JPlace, currently we only move the single height cells to minimize the impact to the given placement.

2. For passing internal-only data in LEF/DEF, the parser is done in-house, which will not be as complete as the one provided by Cadence. For this reason, the user may encounter some parser errors in trying our tool in the beginning. Definitely, this kind of issues will be fixed easily if it dose occur.